Preliminary SiC MOSFET Gate-Cracking Modeling under Short-Circuit Based on Rankine's Damage Energetic Approach Using a Wide Temperature-Range Elastoplastic 2D Simulation [Abstract] - Les productions scientifiques du groupe CS du laboratoire plasma et conversion d’énergie
Communication Dans Un Congrès Année : 2024

Preliminary SiC MOSFET Gate-Cracking Modeling under Short-Circuit Based on Rankine's Damage Energetic Approach Using a Wide Temperature-Range Elastoplastic 2D Simulation [Abstract]

Mustafa Shqair
Emmanuel Sarraute
Frédéric Richardeau

Résumé

For the first time, a structural physical modeling of the Intermediate-Layer-Dielectric (ILD) cracking in a planar-gate SiC MOSFET under short-pulse short-circuit is proposed. This new approach is based on Rankine's damage energetic description, relying on the SiO2 mechanical properties. Using a complete 2D high-temperature range electrothermal-metallurgical and elastoplastic-mechanical SiC MOSFET model, Rankine's sub-model is successfully implemented. The first results allow the extraction of crack penetration depth in a single pulse, prefiguring the average critical cycles number estimation to a possible complete destructive ILD fracture.
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Dates et versions

hal-04713129 , version 1 (03-10-2024)

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  • HAL Id : hal-04713129 , version 1

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Mustafa Shqair, Emmanuel Sarraute, Frédéric Richardeau. Preliminary SiC MOSFET Gate-Cracking Modeling under Short-Circuit Based on Rankine's Damage Energetic Approach Using a Wide Temperature-Range Elastoplastic 2D Simulation [Abstract]. 35th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis - ESREF 2024, Sep 2024, Parma, Italy. ⟨hal-04713129⟩
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